The invention is directed to an integrated circuit arrangement for voltage control of the gain of a field effect transistor having at least two gate electrodes. The first gate electrode forms the signal input and the second gate electrode forms the DC voltage control input.
Field effect transistors (FETs) having two gate electrodes (FET tetrodes) are utilized in controllable amplifier circuits (cascade circuits). The first gate electrode G1 is employed as signal input and the second gate electrode G2, by contrast, is employed as a DC voltage control input. In a circuit arrangement having fixed source and G1 potentials, only the drain current drops greatly with G2 given gain regulation, and operating points occur which lead to great signal distortions.
As may be seen from FIG. 2, this disadvantage can be avoided in a traditional way in that the source terminal of a field effect transistor T.sub.1 comprising two gate electrodes G.sub.1 and G.sub.2 is only grounded in terms of alternating current (C.sub.S), but has its DC voltage potential shifted in current-dependent manner, namely on the basis of a current divider having R.sub.1 and R.sub.2. Given regulation over the second gate electrode G.sub.2, the drain current drops and thus the voltage drop-off via R.sub.2, i.e. the source potential, drops. During regulation, the voltage difference between the first gate electrode G.sub.1 and the source electrode S is thereby modified such that operating points that lead to non-linear signal distortions are largely avoided. Simultaneously, the lowering of the drain current is thereby opposed. The applied operating voltage is referenced U.sub.B and the control voltage is referenced U.sub.R. The signal input is provided with reference numeral 1 and the signal output is provided with reference numeral 2.